Mr. Niraj Kumar

Assistant Professor

Interest Area(s)

  • VLSI Design
  • Radiation Hardened Circuits
  • Digital IC Design
  • CMOS Layout Design
  • Low Power VLSI
  • FPGA Design and Verification
  • Digital Electronics
  • Semiconductor Devices
  • Memory Cell and Latch Architecture

Mr. Niraj Kumar is a researcher and academician specializing in VLSI Design and Digital Electronics, currently pursuing his Ph.D. (Thesis Submitted) from Delhi Technological University (DTU), Delhi. His research focuses on energy-efficient and radiation-tolerant latch circuits for space applications. He possesses expertise in Digital IC Design, CMOS Layout, FPGA implementation, and EDA tools such as Cadence Virtuoso, H-Spice, LT-Spice, and Xilinx Vivado. He has published research papers in reputed SCIE-indexed journals and international conferences. With teaching experience at reputed institutions, he is dedicated to practical learning, innovation, and mentoring students in emerging semiconductor and VLSI technologies. 

  • B.Sc. (Hons.) Electronics, B.Tech. (ECE), M.Tech. (VLSI Design), Ph.D. (VLSI Design) (Thesis Submitted)
  • Dr. K. N. Modi Institute of Engineering & Technology, Uttar Pradesh, India; 2 Months 
  • Lloyd Institute of Engineering & Technology, Greater Noida, India. 
  • SCI Journals:
    1. N. Kumar, C. I. Kumar, and N. Pandey, "High-performance radiation hardened latch using Schmitt trigger," Integration, the VLSI Journal, 2025. https://doi.org/10.1016/j.vlsi.2025.102478.
    2. N. Kumar, C. I. Kumar, and N. Pandey, "High-performance and robust triple-node-upset radiation hardened latch design," AEÜ – Int. J. Electron. Commun., vol. 201, July 2025. https://doi.org/10.1016/j.aeue.2025.155977. 
  • N. Kumar, N. Pandey, and C. I. Kumar, "High Performance Double Node Upset Radiation Hardened Latch in 7 nm FinFET," 2025 10th Int. Conf. Commun. Electron. Syst., pp. 589–594, 2025. https://doi.org/10.1109/ICCES67310.2025.11337000.
  • N. Kumar, N. Pandey, and C. I. Kumar, "Schmitt Trigger Based Compact Radiation Hardened Latch," 2025 IEEE 4th Int. Conf. Adv. Technol., pp. 1–7, 2025. https://doi.org/10.1109/ICONAT66879.2025.11362702. 
  • Research work focused on 'Design of Energy-Efficient and Radiation-Tolerant Latches for Space Applications' during Ph.D. at DTU.
  • Published two SCIE-indexed journal papers in reputed international journals.
  • Presented two research papers in IEEE international conferences.
  • Received two Research Excellence Awards for academic and research contributions.
  • GATE qualified for five consecutive years (2017–2021).
  • Completed Advanced VLSI Design training from Maven Silicon, Bengaluru.
  • Implemented 1D-DCT architecture using FPGA and Verilog during M.Tech. project work.
  • NCC 'C' Certificate holder.